1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a thin film transistor (TFT) and a method for manufacturing the same suitable for improving device characteristics by using a self-align technology.
2. Discussion of the Related Art
Instead of a CMOS load transistor or a load resistor, a TFT is used in an SRAM of over a 16M class or a 4M class. It is used as a switching device for switching picture data signals in each pixel region in an LCD.
Since a PMOS TFT is used as a load transistor in an SRAM cell, off-current of the load transistor is reduced and on-current is increased. Thus, power consumption of an SRAM cell is reduced and memory characteristic is enhanced, thereby proving an SRAM cell having a high quality. An offset region of a TFT is an important factor to stabilize an SRAM cell. It is significantly important how precisely offset regions are formed during its process.
A background art TFT and a method for manufacturing the same will be described with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view showing a structure of a TFT, which includes an insulating layer 21, first and second gate electrode 22a and 22b formed on the insulating layer 21 to be spaced apart from each other, a source electrode S overlapping an edge portion of the first gate electrode 22a, a drain electrode D connected to the second gate electrode 22b through a contact hole and spaced apart from the first gate electrode 22a, and a metal layer 27 connected to the source electrode S and the second gate electrode 22b. In this case, a polysilicon layer used as a channel region and an offset region is between the source electrode S and the drain electrode D. The second gate electrode 22b is used as a drain.
FIGS. 2A to 2F are cross-sectional views showing process steps of a background art method for fabricating the above-described TFT.
Referring to FIG. 2A, a polysilicon layer is formed on an insulating layer 21 and selectively removed to form first and second gate electrodes 22a and 22b.
Referring to FIG. 2B, a gate insulating film 23 is deposited on the insulating layer 21 including the first and second gate electrodes 22a and 22b.
Referring to FIG. 2C, a predetermined area of the gate insulating film 23 on the second gate electrode 22b is removed so that the surface of the second gate electrode 22b is exposed.
Referring to FIG. 2D, a polysilicon layer 24 for source and drain electrodes is formed and then an ion-injecting process for adjusting threshold voltage is performed.
Referring to FIG. 2E, a photoresist film is coated on the entire surface and patterned to form a mask pattern 25. An ion-injecting process is performed by using the mask pattern 25 to form source and drain regions S and D.
Referring to FIG. 2F, an interlayer insulating film 26 is deposited, and the interlayer insulating layer 26 and the gate insulating film 23 are patterned to expose predetermined areas of the second gate electrode 22b and the source electrode S. Metal layers 27 are formed. At this time, the source region S partially overlaps the first gate electrode 22a. The drain region D is formed spaced apart from the first gate electrode 22a. A channel region I and an offset region II are all formed between the source and drain regions S and D.
The background art TFT and the method for manufacturing the same have the following problems.
A photo mask process is required for forming an offset region and misalignment of photoresist changes channel region and offset region. This change of channel region and offset region deteriorates device reliability and the stability of cells an SRAM.